In the past, the designer of computer logic with embedded arrays has had complete flexibility in arranging logic circuitry to implement systems and subsystem logic functions in central processing units, channels and control units employed in digital computing apparatus. A significant variety of design implementations has resulted from the exercise of this flexibility. Each of these implementations has its own special dependency on the ac characteristics of the individual circuits employed in the system.
The independence and flexibility characterizing the arrangements of the designer often led to unexpected system timing problems, complicated and complex problems in testing the logic around arrays themself, and a significant complexity and detail required for educating the field service personnel for such computing systems. However, it had the advantage of permitting the designer to use all techniques to obtain the best performance by employing the fewest number of circuits. The interface between the logic designer and the component manufacturer was reasonably well defined and the approach of the past could be supported in component manufacturing since the ac parameters such as rise time, fall time, individual circuit delay, access time, etc., could rather readily be tested. The arrays were tested as arrays on cards which had only arrays and the logic cards, which did not have arrays, were tested as logic cards on logic testers.
With the advent of large scale integration, however, this well defined and reliably tested interface no longer exists. It has become impossible or impractical to test each circuit for all of the well known ac circuit parameters and to test each array for all of its well known ac circuit parameters.
As a result, it is necessary to partition and divide logic systems and subsystems into functional units having characteristics that are substantially insensitive to these parameters. Large scale integration provides the ability for the logic designer as well as the component manufacturer to utilize the capacity for placing hundreds of circuits or a complete array on a single chip of semiconductive material. Such an ability offers the potential for reducing power, increasing speed, and significantly reducing the cost of digital networks.
Unfortunately, a number of serious considerations are involved before this potential can be achieved. For example, in a medium sized computing system having approximately 40,000 individual circuits plus arrays, it has not been uncommon to effect 1500 or more engineering changes during the development period for product. It is readily apparent that the implementation of such a significant number of engineering changes approaches the impossible when dealing with the lowest level modular unit of a computer which has hundreds of circuits contained within it.
Another area which must be considered as technology moves into the fabrication of large scale integrated functional units is the product testing required prior to its incorporation into a computing system. The subsequent diagnostic tests performed during field servicing as well as the simulation that is performed during design and manufacturing are factors for consideration in fabricating such functional units.
In the past, each individual array has been tested for the usual and normal ac and dc parameters. Access to the modular unit for applying the input test condition and measuring the output responses has been achieved through a fixed number of input/output connection pins. Furthermore, the arrays and logic were not mixed. However, in the realm of large scale integrated functional units, the same number of input/output pins are available, but there is considerably more circuitry mixed with arrays.
Thus, in a typical module containing 100 chips with logic chips having up to 600 (averaging 400) circuits and 25 array chips, the module would contain at least 40,000 circuits and 25 arrays. Parametric testing of such a unit is not possible. DC testing and AC testing all of the logic which does not feed arrays or is not fed from arrays can be performed by the structure methods and techniques described in the afore-identified U.S. Pat. Nos. 3,761,695, 3,783,254 and 3,784,907 granted to Edward B. Eichelberger and assigned to the same assignee. If functional tests of the arrays are attempted on such a unit, having the prior art logical design configurations, the extent of test coverage of logic immediately around the array and for the array would be significantly low and the level of reliability for use in a computing system would also be significantly low. Accordingly, provision must be made for eliminating the dependencies of the past. Current logic/array systems must be avoided and new logic/array organizations must be utilized in computing systems if the advantages of large scale integration are to be optimized. Testing of these logic/array systems must be performed in a functional manner on these new logical units, be it at the chip level, the module level, or other level. This testing is accomplished by automatically generating tests that assume the proper operation of every logic element in the unit.